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XIO2221 Datasheet(PDF) 6 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 196 page  XIO2221 SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 www.ti.com 8.21 Interrupt Event Register ................................................................................................. 145 8.22 Interrupt Mask Register ................................................................................................. 147 8.23 Isochronous Transmit Interrupt Event Register ...................................................................... 150 8.24 Isochronous Transmit Interrupt Mask Register ...................................................................... 151 8.25 Isochronous Receive Interrupt Event Register ....................................................................... 151 8.26 Isochronous Receive Interrupt Mask Register ....................................................................... 152 8.27 Initial Bandwidth Available Register ................................................................................... 152 8.28 Initial Channels Available High Register .............................................................................. 153 8.29 Initial Channels Available Low Register ............................................................................... 153 8.30 Fairness Control Register ............................................................................................... 154 8.31 Link Control Register .................................................................................................... 155 8.32 Node Identification Register ............................................................................................ 156 8.33 PHY Control Register .................................................................................................... 157 8.34 Isochronous Cycle Timer Register ..................................................................................... 158 8.35 Asynchronous Request Filter High Register ......................................................................... 158 8.36 Asynchronous Request Filter Low Register .......................................................................... 161 8.37 Physical Request Filter High Register ................................................................................. 161 8.38 Physical Request Filter Low Register ................................................................................. 164 8.39 Physical Upper Bound Register (Optional Register) ................................................................ 164 8.40 Asynchronous Context Control Register .............................................................................. 165 8.41 Asynchronous Context Command Pointer Register ................................................................. 166 8.42 Isochronous Transmit Context Control Register ..................................................................... 167 8.43 Isochronous Transmit Context Command Pointer Register ........................................................ 168 8.44 Isochronous Receive Context Control Register ...................................................................... 168 8.45 Isochronous Receive Context Command Pointer Register ......................................................... 170 8.46 Isochronous Receive Context Match Register ....................................................................... 170 9 1394 OHCI Memory-Mapped TI Extension Register Space ..................................................... 172 9.1 Digital Video (DV) and MPEG2 Timestamp Enhancements ....................................................... 172 9.2 Isochronous Receive Digital Video Enhancements ................................................................. 173 9.3 Isochronous Receive Digital Video Enhancement Registers ....................................................... 173 9.4 Link Enhancement Control Registers ................................................................................. 174 9.5 Timestamp Offset Registers ............................................................................................ 176 10 Physical Layer (PHY) Section ............................................................................................ 177 10.1 PHY Section Register Configuration .................................................................................. 178 10.2 PHY Section Application Information .................................................................................. 185 10.2.1 Power Class Programming .................................................................................. 185 10.2.2 Power-Up Reset ............................................................................................... 186 10.2.3 Crystal Oscillator Selection .................................................................................. 186 10.2.4 Bus Reset ...................................................................................................... 187 11 Electrical Characteristics .................................................................................................. 188 11.1 Absolute Maximum Ratings ............................................................................................. 188 11.2 Recommended Operating Conditions ................................................................................. 188 11.3 PCIe Differential Transmitter Output Ranges ........................................................................ 188 11.4 PCIe Differential Receiver Input Ranges ............................................................................. 190 11.5 PCIe Differential Reference Clock Input Ranges .................................................................... 191 11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) .............................. 191 6 Contents Copyright © 2009–2010, Texas Instruments Incorporated |
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