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TPS65270 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65270 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page TPS65270 SLVSAX7C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Voltage range at VIN1, VIN2, LX1, LX2 –0.3 to 18 V Voltage range at LX1, LX2 (maximum withstand voltage transient < 10 ns) –1 to 18 V Voltage at BST1, BST2, referenced to LX1, LX2 pin –0.3 to 7 V Voltage at VCC, EN1, EN2, COMP1, COMP2, LOW_P –0.3 to 7 V Voltage at SS1, SS2, FB1, FB2, ROSC –0.3 to 3.6 V Voltage at AGND, GND –0.3 to 0.3 V TJ Operating virtual junction temperature range –40 to 125 °C TSTG Storage temperature range –55 to 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input operating voltage 4.5 18 V TA Ambient temperature –40 85 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT Human body model (HBM) 2000 V Charge device model (CDM) 500 V PACKAGE DISSIPATION RATINGS (1) (2) (3) TA = 25°C TA = 55°C TA = 85°C PACKAGE θJA (°C/W) θJC (°C/W) POWER RATING (W) POWER RATING (W) POWER RATING (W) PWP 32.6 10 3.07 2.15 1.23 RGE 32.6 10 3.07 2.15 1.23 (1) This assumes a JEDEC JESD 51-5 standard board with thermal vias with High K profile - See Texas Instruments application report (SLMA002) regarding thermal characteristics of the PowerPAD™ package. (2) This assumes junction to exposed PAD. (3) Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement: (a) Top layer: 2 Oz Cu, 6.7% coverage (b) Layer 2: 1 Oz Cu, 90% coverage (c) Layer 3: 1 Oz Cu, 90% coverage (d) Bottom layer: 2 Oz Cu, 20% coverage 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TPS65270 |
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