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SN74HC74MPWREP Datasheet(PDF) 1 Page - Texas Instruments |
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SN74HC74MPWREP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 12 page 1 FEATURES DESCRIPTION/ORDERING INFORMATION SN74HC74-EP DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET SCLS710 – MARCH 2008 www.ti.com • Controlled Baseline • Wide Operating Voltage Range of 2 V to 6 V – One Assembly Site • Outputs Can Drive up to 10 LSTTL Loads – One Test Site • Low Power Consumption, 80 µA Max I CC – One Fabrication Site • Typical t pd = 15 ns • Extended Temperature Performance of –55°C • ±4 mA Output Drive at 5 V to 125 °C • Low Input Current of 1 mA Max • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. The SN74HC74 device contains two independent D-type positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION(1) TA PACKAGE(2) ODERABLE PART NUMBER TOP-SIDE MARKING SOIC – D Reel of 2500 SN74HC74MDREP HC74MEP –55 °C to 125°C TSSOP – PW Reel of 2000 SN74HC74MPWREP HC74MEP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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