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PCI4515AGHK Datasheet(PDF) 1 Page - Texas Instruments

Part # PCI4515AGHK
Description  Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port PHY/Link-Layer Controller
Download  6 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCI4515AGHK Datasheet(HTML) 1 Page - Texas Instruments

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FEATURES
PCI4515A
SLLA241 – JUNE 2006
Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port
PHY/Link-Layer Controller
Fully Compliant With Provisions of IEEE Std
1394-1995 for a High-Performance Serial Bus
PC Card Standard 8.1 Compliant
and IEEE Std 1394a-2000
PCI Bus Power Management Interface
Fully Compliant With 1394 Open Host
Specification 1.1 Compliant
Controller Interface Specification 1.1
Advanced Configuration and Power Interface
Full IEEE Std 1394a-2000 Support Includes:
(ACPI) Specification 2.0 Compliant
Connection Debounce, Arbitrated Short
PCI Local Bus Specification Revision 2.3
Reset, Multispeed Concatenation, Arbitration
Compliant
Acceleration, Fly-by Concatenation, And Port
PC 98/99 and PC2001 Compliant
Disable/Suspend/Resume
Windows Logo Program 2.0 Compliant
Power-Down Features to Conserve Energy in
PCI Bus Interface Specification for
Battery-Powered Applications Include:
PCI-to-CardBus Bridges
Automatic Device Power Down During
1.5-V Core Logic and 3.3-V I/O Cells With
Suspend, PCI Power Management for
Internal Voltage Regulator to Generate 1.5-V
Link-Layer, and Inactive Ports Powered
Core VCC
Down, Ultralow-Power Sleep Mode
Universal PCI Interfaces Compatible With
A IEEE Std 1394a-2000 Fully Compliant Cable
3.3-V and 5-V PCI Signaling Environments
Port at 100M Bits/s, 200M Bits/s, and 400M
Bits/s
Supports PC Card or CardBus With Hot
Insertion and Removal
Cable Port Monitors Line Conditions for
Active Connection to Remote Node
Supports 132-MBPS Burst Transfers to
Maximize Data Throughput on Both the PCI
Cable Power Presence Monitoring
Bus and the CardBus
Separate Cable Bias (TPBIAS) for the Port
Supports Serialized IRQ With PCI Interrupts
Physical Write Posting of Up To Three
Programmable Multifunction Terminals
Outstanding Transactions
Many Interrupt Modes Supported
PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency
Serial ROM Interface for Loading Subsystem
ID and Subsystem Vendor ID
External Cycle Timer Control for Customized
Synchronization
ExCA-Compatible Registers Are Mapped in
Memory or I/O Space
Extended Resume Signaling for Compatibility
With Legacy DV Components
Intel 82365SL-DF Register Compatible
PHY-Link Logic Performs System
Supports Ring Indicate, SUSPEND, and PCI
Initialization and Arbitration Functions
CLKRUN Protocols and PCI Bus Lock (LOCK)
PHY-Link Encode and Decode Functions
Provides VGA/Palette Memory and I/O, and
Included for Data-Strobe Bit Level Encoding
Subtractive Decoding Options, LED Activity
Terminals
PHY-Link Incoming Data Resynchronized to
Local Clock
Fully Interoperable With FireWire™ and
i.LINK™ Implementations of IEEE Std 1394
Low-Cost 24.576-MHz Crystal Provides
Transmit and Receive Data at 100M Bits/s,
Compliant With Intel Mobile Power Guideline
200M Bits/s, and 400M Bits/s
2000
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Inc..
i.LINK is a trademark of Sony Corporation of America..
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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