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SN75LVDS84ADGGRG4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN75LVDS84ADGGRG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 17 page SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D 21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput D Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI D 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs D Operates From a Single 3.3-V Supply and 89 mW (Typ) D Ultralow-Power 3.3-V CMOS Version of the SN75LVDS84. Power Consumption About One Third of the ’LVDS84 D Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20 Mil Terminal Pitch D Consumes Less Than 0.54 mW When Disabled D Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz D No External Components Required for PLL D Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard D SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency D Improved Replacement for SN75LVDS84 and NSC’s DS90CF363A 3-V Device D Available in Q-Temp Automotive High Reliability Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards description The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 NC D13 D14 GND D15 D16 D17 VCC D18 D19 GND D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20 DGG PACKAGE (TOP VIEW) NC – Not Connected |
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