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SN65LV1023AMDBREP Datasheet(PDF) 1 Page - Texas Instruments |
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SN65LV1023AMDBREP Datasheet(HTML) 1 Page - Texas Instruments |
1 / 25 page www.ti.com FEATURES DESCRIPTION SN65LV1023A-EP SN65LV1224B-EP SGLS358 – SEPTEMBER 2006 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz • Controlled Baseline System Clock – One Assembly/Test Site, One Fabrication • Pin-Compatible Superset of Site DS92LV1023/DS92LV1224 • Extended Temperature Performance of –55 °C • Chipset (Serializer/Deserializer) Power to 125 °C Consumption <450 mW (Typ) at 66 MHz • Enhanced Diminishing Manufacturing • Synchronization Mode for Faster Lock Sources (DMS) Support • Lock Indicator • Enhanced Product-Change Notification • No External Components Required for PLL • Qualification Pedigree (1) • 28-Pin SSOP and Space Saving 5 × 5 mm (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an QFN Packages Available extended temperature range. This includes, but is not limited • Programmable Edge Trigger on Clock to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, • Flow-Through Pinout for Easy PCB Layout electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –55 °C to 125 °C. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING -55 °C to 125°C SSOP - DB Reel of 2000 SN65LV1023AMDBREP LV1023AMEP -55 °C to 125°C SSOP - DB Reel of 2000 SN65LV1224BMDBREP LV1224BMEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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