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TMS320C6743CZKBT3 Datasheet(PDF) 7 Page - Texas Instruments |
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TMS320C6743CZKBT3 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 153 page  TMS320C6743 www.ti.com SPRS565B – APRIL 2009 – REVISED JUNE 2011 Revision History (continued) See ADDITIONS/MODIFICATIONS/DELETIONS Section 5.6.1 Figure 5-9, PLL Topology: PLL Device-Specific • Updated to remove OBSCLK area. Information Table 5-4, Allowed PLL Operating Conditions: • Updated PLLRST, PLLOUT, and POSTDIV MIN values. • Updated Lock time MAX equation. • Updated PLLREF MAX value. • Updated table note. Table 5-6, PLL Controller 0 Registers: • Changed addresses 0x01C1 1104 and 0x01C1 1124 to Reserved. Section 5.6.2 Table 5-5, System PLLC0 Output Clocks: Device Clock Generation • Added SPI0 for SYSCLK2. • Added I2C0 for AUXCLK. Section 5.7 Table 5-7, C6743 DSP Interrupts: DSP Interrupts • Added PRUSS interrupts (6, 17, 22, 35, 39, 44, 50, 66). Section 5.8 Section 5.8.2, GPIO Peripheral Input/Output Electrical Data/Timing: General-Purpose Input/Output • Removed "For example,..." from the C=SYSCLK4 note for Table 5-10 and Table 5-11. (GPIO) Section 5.8.3, GPIO Peripheral External Interrupts Electrical Data/Timing : • Removed "For example,..." from the C=SYSCLK4 note for Table 5-12. Section 5.9 Table 5-17, EDMA Events: EDMA • Updated Channel Controller event 20 to PRU_EVTOUT6 and event 21 to PRU_EVTOUT7. Section 5.10.4 Table 5-19: EMIFA Electrical Data/Timing • Added tc(CLK) parameter. Figure 5-13, Asynchronous Memory Read Timing for EMIFA, through Figure 5-16, EMA_WAIT Write Timing Requirements: • Added EMA_A_RW. • Changed EMA_CE[5:2] to EMA_CS[5:2] • Removed unused parameters from Figure 5-13 and Figure 5-14. Section 5.11 Section 5.11.1 External Memory Interface B • Updated bullets for clarification. (EMIFB) Table 5-21, EMIFB Supported SDRAM Configurations: • Corrected note: changed EMIFA to EMIFB. Section 5.12 Added section. Memory Protection Units Section 5.13.2 Table 5-30, Switching Characteristics Over Recommended Operating Conditions for MMC/SD MMC/SD Electrical Module: Data/Timing • Updated td(CLKL-DAT) MAX value. Section 5.14.2 Table 5-35, RMII Timing Requirements: EMAC Electrical Data/Timing • Changed REF_CLK to RMII_MHZ_50_CLK. • Added table note regarding jitter tolerance. Table 5-36, RMII Switching Characteristics • Corrected table title. • Changed REF_CLK to RMII_MHZ_50_CLK. Section 5.15 Section 5.15.2, Management Data Input/Output (MDIO) Electrical Data/Timing: Management Data Input/Output • Changed MDIO to MDIO_D for data input/output. (MDIO) • Changed MDCLK to MDIO_CLK. • Updated th(MDIO_CLKH-MDIO) MIN value in Table 5-38. Section 5.16 Table 5-40, C6743 McASP Configurations: Multichannel Audio Serial Ports • Removed AMUTE0 from list of McASP0 pins. (McASP0, McASP1) Section 5.16.2, McASP Electrical Data/Timing: • Updated MIN and MAX values in tables for McASP0 and McASP1. Copyright © 2009–2011, Texas Instruments Incorporated TMS320C6743 Fixed/Floating-Point Digital Signal Processor 7 Submit Documentation Feedback Product Folder Link(s): TMS320C6743 |
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