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SE370C702 Datasheet(PDF) 5 Page - Texas Instruments |
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SE370C702 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 50 page TMS370Cx0x 8-BIT MICROCONTROLLER SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 description (continued) The TMS370Cx0x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family compact development tool (CDT ™) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx0x into an ever-increasing number of complex applications. The application source code can be written in assembly and C-language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use through extensive menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle. The TMS370Cx0x family together with the TMS370 family CDT370, design kit, starter kit, software tools, the SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer. central processing unit (CPU) The CPU used on the TMS370Cx0x device is the high-performance 8-bit TMS370 CPU module. The ’x0x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x0x instruction map is shown in Table 15 in the TMS370Cx0x instruction set overview section. The ’370Cx0x CPU architecture provides the following components: CPU registers: D A stack pointer that points to the last entry in the memory stack D A status register that monitors the operation of the instructions and contains the global interrupt enable bits D A program counter (PC) that points to the memory location of the next instruction to be executed Figure 1 illustrates the CPU registers and memory blocks. CDT is a trademark of Texas Instruments Incorporated. |
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