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ICE40HX4K-CB225 Datasheet(PDF) 7 Page - Lattice Semiconductor |
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ICE40HX4K-CB225 Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 12 page iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family Lattice Semiconductor Corporation (1.31, 30-MAR-2012) www.latticesemi.com/ 7 Programmable Input/Output (PIO) Block Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths shown in Figure 7 and Figure 8. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The iCEcube2 development software reports timing adjustments for other I/O standards. Figure 7: Programmable I/O (PIO) Pad-to-Pad Timing Circuit PAD PIO PAD PIO Figure 8: Programmable I/O (PIO) Sequential Timing Circuit PAD PIO GBIN GBUF PAD PIO D Q INFF D Q OUTFF Table 9: Typical Programmable Input/Output (PIO) Timing (LVCMOS25) Nominal VCC 1.2 V units Description Typ. Synchronous Output Paths tOCKO OUTFF clock input PIO output Delay from clock input on OUTFF output flip-flop to PIO output pad. 3.1 ns tGBCKIO GBIN input OUTFF clock input Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network to clock input on the PIO OUTFF output flip-flop. 1.4 ns Synchronous Input Paths tSUPDIN PIO input GBIN input Setup time on PIO input pin to INFF input flip-flop before active clock edge on GBIN input, including interconnect delay. 0 ns tHDPDIN GBIN input PIO input Hold time on PIO input to INFF input flip-flop after active clock edge on the GBIN input, including interconnect delay. 1.6 ns Pad to Pad tPADIN PIO input Inter- connect Asynchronous delay from PIO input pad to adjacent interconnect. 1.8 ns tPADO Inter- connect PIO output Asynchronous delay from adjacent interconnect to PIO output pad including interconnect delay. 3.4 ns |
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