SN65LVCP402

SWITCHING CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

0 dB preemphasis

Intrinsic deterministic device (PREx_x = 0);

4 Gbps

30

ps

See Figure 8 for the test

pattern

circuit.

1.25 Gbps

Over 20-inch

7

DJ

FR4 trace

0 dB preemphasis

Absolute deterministic

(PREx_x = 0);

4 Gbps

ps

See Figure 8 for the test

pattern

Over FR4

circuit.

trace 2-inch

20

to 20 inches

long

(5)

Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation

peak-to-peak deterministic jitter of the pattern generator driving the device.

(6)

The SN65LVCP402 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the

LVCP402 typically reduces jitter by 60 ps from the device input to the device output.

(7)

Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP402 output. The value is a real measured

value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated

Table 2. Preemphasis Controls Settings

OUTPUT

TYPICAL FR4

PREEMPHASIS

TRACE LENGTH

DE-EMPHASIZED

PRE-EMPHASIZED

LEVEL IN dB

0

0

0 dB

1200

1200

10 inches of FR4 trace

0

1

3 dB

850

1200

20 inches of FR4 trace

1

0

6 dB

600

1200

30 inches of FR4 trace

1

1

9 dB

425

1200

40 inches of FR4 trace

(1)

x = 1 or 2

Table 2. Receive Equalization Settings

EQ

Equalization

Typical Line Trace

1

5 dB

25 inches of FR4

0

12 dB

43 inches of FR4

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Product Folder Link(s): SN65LVCP402