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SM320LF2407-EP Datasheet(PDF) 49 Page - Texas Instruments |
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SM320LF2407-EP Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 112 page  SM320LF2407AEP DSP CONTROLLERS SGUS036B − JULY 2003 − REVISED OCTOBER 2003 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 external memory interface (LF2407A) The LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data, and I/O spaces. On-chip memory, when enabled, occupies some of this off-chip range. The CPU of the LF2407A schedules a program fetch, data read, and data write on the same machine cycle. This is because from on-chip memory, the CPU can execute all three of these operations in the same cycle. However, the external interface multiplexes the internal buses to one address bus and one data bus. The external interface sequences these operations to complete first the data write, then the data read, and finally the program read. The LF2407A supports a wide range of system interfacing requirements. Program, data, and I/O address spaces provide interface to memory and I/O, thereby maximizing system throughput. The full 16-bit address and data buses, along with the PS, DS, and IS space-select signals, allow addressing of 64K 16-bit words in program, data, and I/O space. Since on-chip peripheral registers occupy positions of data-memory space (7000−7FFF), the externally addressable data-memory space is 32K 16-bit words (8000−FFFF). Note that the global memory space of the C2xx core is not used for 240xA DSP devices. Therefore, the global memory allocation register (GREG) is reserved for all these devices. Input/output (I/O) design is simplified by having I/O space treated the same way as memory. I/O devices are accessed in the I/O address space using the processor’s external address and data buses in the same manner as memory-mapped devices. The LF2407A external parallel interface provides various control signals to facilitate interfacing to the device. The R/ W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal provides a timing reference for all external cycles. For convenience, the device also provides the RD and the WE output signals, which indicate a read cycle and a write cycle, respectively, along with timing information for those cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to the LF2407A. The 2407A provides RD and W/R signals to help the zero-wait-state external memory interface. At higher CLKOUT speeds, RD may not meet the slow memory device’s timing. In such instances, the W/R signal could be used as an alternative signal with some tradeoffs. See the timings for details. The LF2407A supports zero-wait-state reads on the external interface. However, to avoid bus conflicts, writes take two cycles. This allows the LF2407A to buffer the transition of the data bus from input to output (or from output to input) by a half cycle. In most systems, the LF2407A ratio of reads to writes is significantly large to minimize the overhead of the extra cycle on writes. wait-state generation Wait-state generation is incorporated in the LF2407A without any external hardware for interfacing the LF2407A with slower off-chip memory and I/O devices. Adding wait states lengthens the time the CPU waits for external memory or an external I/O port to respond when the CPU reads from or writes to that external memory or I/O port. Specifically, the CPU waits one extra cycle (one CLKOUT cycle) for every wait state. The wait states operate on CLKOUT cycle boundaries. To avoid bus conflicts, writes from the LF2407A always take at least two CLKOUT cycles. The LF2407A offers two options for generating wait states: D READY Signal. With the READY signal, you can externally generate any number of wait states. The READY pin has no effect on accesses to internal memory. D On-Chip Wait-State Generator. With this generator, you can generate zero to seven wait states. |
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