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RM48L740 Datasheet(PDF) 9 Page - Texas Instruments |
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RM48L740 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 152 page RM48L940 RM48L740 RM48L540 www.ti.com SPNS175 – SEPTEMBER 2011 Table 1-2. Device ID Bit Allocation Register Field Descriptions Bit Field Value Description 31 CP15 Indicates the presence of coprocessor 15 1 CP15 present 30-17 UNIQUE ID 10101 Silicon version (revision) bits. This bitfield holds a unique number for a dedicated device configuration (die). 16-13 TECH Process technology on which the device is manufactured. 0101 F021 12 I/O VOLTAGE I/O voltage of the device. 0 I/O are 3.3v 11 PERIPHERAL Peripheral Parity PARITY 1 Parity on peripheral memories 10-9 FLASH ECC Flash ECC 10 Program memory with ECC 8 RAM ECC Indicates if RAM memory ECC is present. 1 ECC implemented 7-3 REVISION Revision of the Device. 2-0 101 The platform family ID is always 0b101 1.1.3.2 Die Identification Registers The four die ID registers at addresses 0xFFFFE1F0, 0xFFFFE1F4, 0xFFFFE1F8 and FFFFE1FC form a 128-bit dieid with the information as shown in Table Table 1-3. Table 1-3. Die-ID Registers Item # of Bits Bit Location X Coord. on Wafer 8 7..0 Y Coord. on Wafer 8 15..8 Wafer # 6 21..16 Lot # 24 45..22 Reserved 82 127..46 Copyright © 2011, Texas Instruments Incorporated Contents 9 Submit Documentation Feedback focus.ti.com: RM48L940 RM48L740 RM48L540 |
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