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OMAPL138B Datasheet(PDF) 1 Page - Texas Instruments |
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OMAPL138B Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 282 page  OMAPL138B-EP www.ti.com SPRS815B – DECEMBER 2011 – REVISED MARCH 2012 OMAPL138B C6-Integra™ DSP+ARM® Processor Check for Samples: OMAPL138B-EP 1 OMAPL138B C6-Integra™ DSP+ARM® Processor 1.1 Features 1 • Highlights • C674x Two Level Cache Memory Architecture – Dual Core SoC – 32K-Byte L1P Program RAM/Cache • 345-MHz ARM926EJ-S™ RISC MPU – 32K-Byte L1D Data RAM/Cache • 345-MHz C674x Fixed/Floating-Point VLIW – 256K-Byte L2 Unified Mapped RAM/Cache DSP – Flexible RAM/Cache Partition (L1 and L2) – Supports TI’s Basic Secure Boot • Enhanced Direct-Memory-Access Controller 3 – Enhanced Direct-Memory-Access Controller (EDMA3): (EDMA3) – 2 Channel Controllers – Serial ATA (SATA) Controller – 3 Transfer Controllers – DDR2/Mobile DDR Memory Controller – 64 Independent DMA Channels – Two Multimedia Card (MMC)/Secure Digital – 16 Quick DMA Channels (SD) Card Interface – Programmable Transfer Burst Size – LCD Controller • TMS320C674x Floating-Point VLIW DSP Core – Video Port Interface (VPIF) – Load-Store Architecture With Non-Aligned – 10/100 Mb/s Ethernet MAC (EMAC) Support – Programmable Real-Time Unit Subsystem – 64 General-Purpose Registers (32 Bit) – Three Configurable UART Modules – Six ALU (32-/40-Bit) Functional Units – USB 1.1 OHCI (Host) With Integrated PHY • Supports 32-Bit Integer, SP (IEEE Single – One Multichannel Audio Serial Port Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point – Two Multichannel Buffered Serial Ports • Supports up to Four SP Additions Per • Dual Core SoC Clock, Four DP Additions Every 2 Clocks – 345-MHz ARM926EJ-S™ RISC MPU • Supports up to Two Floating Point (SP or – 345-MHz C674x Fixed/Floating-Point VLIW DP) Reciprocal Approximation (RCPxP) DSP and Square-Root Reciprocal • ARM926EJ-S Core Approximation (RSQRxP) Operations Per – 32-Bit and 16-Bit (Thumb®) Instructions Cycle – DSP Instruction Extensions – Two Multiply Functional Units – Single Cycle MAC • Mixed-Precision IEEE Floating Point – ARM® Jazelle® Technology Multiply Supported up to: – EmbeddedICE-RT™ for Real-Time Debug – 2 SP x SP → SP Per Clock • ARM9 Memory Architecture – 2 SP x SP → DP Every Two Clocks – 16K-Byte Instruction Cache – 2 SP x DP → DP Every Three Clocks – 16K-Byte Data Cache – 2 DP x DP → DP Every Four Clocks – 8K-Byte RAM (Vector Table) • Fixed Point Multiply Supports Two 32 x – 64K-Byte ROM 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per • C674x™ Instruction Set Features Clock Cycle, and Complex Multiples – Superset of the C67x+™ and C64x+™ ISAs – Instruction Packing Reduces Code Size – Up to 3648/2746 C674x MIPS/MFLOPS – All Instructions Conditional – Byte-Addressable (8-/16-/32-/64-Bit Data) – Hardware Support for Modulo Loop – 8-Bit Overflow Protection Operation – Bit-Field Extract, Set, Clear – Protected Mode Operation – Normalization, Saturation, Bit-Counting – Exceptions Support for Error Detection and – Compact 16-Bit Instructions 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2011–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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