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FR011L5J Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FR011L5J Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 12 page © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C2 11 Physical Dimensions B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION ASME Y14.5M, 1994 0.10 CA B 0.05 C TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN OPT 1 0.10 C 0.08 C B A C 2.00 2.00 0.05 0.00 0.10 C 2X 2X 0.8 MAX SIDE VIEW SEATING PLANE 0.10 C (0.20) 0.33 0.20 1 3 4 6 4 6 3 1 PIN #1 IDENT 0.65 1.30 1.35 1.05 0.40 TYP 0.65 TYP 0.35 0.25 2.30 1.00 MO-229 DATED AUG/2003 0.61 0.51 0.30 0.66 RECOMMENDED LAND PATTERN OPT 2 4 6 3 1 1.35 (0.475) 1.05 0.40 TYP 0.65 TYP 2.30 1.00 No Traces allowed in this Area Pin #1 location 1.05 0.95 D. DRAWING FILENAME: MKT-MLP06Lrev3. 0.50 0.15 0.50 0.20 0.45 (0.20) 1.00 0.80 6X 6X Figure 20. 6-Lead, Molded Leadless Package (MLP), Dual, Non-JEDEC, 2mm Square, Single-Tied DAP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. |
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