TI380FPAA

PACKETBLASTER

™

SPWS038 – MAY 1997

5

POST OFFICE BOX 1443

Terminal Functions (Continued)

TERMINAL

I/O †

DESCRIPTION

NAME

NO.

I/O †

DESCRIPTION

MAXPL

6

I/O

Low byte of local memory extended address and parity. For the first quarter of a memory cycle, MAXPL

carries the extended address bit AX3; for the second quarter of a memory cycle, MAXPL carries

extended address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for the

low-data byte.

Memory Cycle

1Q

2Q

3Q

4Q

Signal

AX3

AX2

Parity

Parity

MBCLK1

43

I

Local bus clock 1. MBCLK1 is referenced for all local bus transfers.

MBEN

21

O

Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and

MADL buses during the data phase. MBEN is used in conjunction with MDDIR, which selects the buffer

output direction.

H = Buffer output disabled

L

= Buffer output enabled

MBGR

37

I

Local bus grant. MBGR indicates that the FPA has been granted access to the adapter local memory

bus.

MBRQ

34

I/O

Local bus request. MBRQ is used by the FPA to request bus-master access to the adapter local memory

bus. The FPA also monitors MBRQ to allow it to defer to other higher-priority bus requests (see

Note 1).

MCAS

26

O

Column-address strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle

following the row-address portion of the cycle. MCAS is driven low every memory cycle while the column

address is valid on MADL0 – MADL7, MAXPH, and MAXPL, except when one of the following conditions

occurs:

1)

When

the

address

accessed

is

a

TI380C2x

or

TI380C3x

internal

register

(>01.0100 – >01.01FF).

2)

When the address accessed is in the TI380C2x or TI380C3x external device address range

(>01.0200 – >01.02FF). This address range includes the FPA registers.

3)

When the BOOT bit in the SIFACL register is zero and the address accessed is in adapter ROM

address range (>00.0000–>00.FFFE or >1F.0000–>1F.FFFE).

MDDIR

31

I/O

Data direction. MDDIR is used for direction control for bidirectional bus drivers. MDDIR becomes valid

before MBEN becomes active.

H = TI380FPAA memory bus write

L

= TI380FPAA memory bus read

MOE

22

O

Memory output enable. MOE is used to enable the outputs of the DRAM memory during a read cycle.

MOE is high for EPROM or BIA ROM read cycles. MOE remains inactive high to keep DRAM outputs

tri-stated:

1)

When the address read is a TI380C2x or TI380C3x internal register (>01.0100–>01.01FF).

2)

When the address read is in the TI380C2x or TI380C3x external device address range

(>01.0200–>01.02FF). This address range includes the FPA registers.

3)

When the BOOT bit in the SIFACL register is zero and the address read is in adapter

ROM-address range (>00.0000–>00.FFFE or 1F.0000–1F.FFFE).

H= Disable DRAM outputs

L = Enable DRAM outputs

† I = input, O = output

NOTE 1: Pin has an open-collector output. EXTINT0 should have an individual 1-k

Ω pullup resistor. A 4.7-kΩ resistor can lead to transmit

underruns in the adapter system and should not be used. For this reason, a 1-k

Ω resistor is specified.