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TI380C25PGE Datasheet(PDF) 9 Page - Texas Instruments |
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TI380C25PGE Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 71 page  TI380C25 TOKEN-RING COMMPROCESSOR SPWS012 – JANUARY 1995 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Pin Functions (Continued) PIN I/O† DESCRIPTION NAME NO. I/O† DESCRIPTION SALE 64 O System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched address. SBBSY 50 I System bus busy. The TI380C25 samples the value on SBBSY during arbitration (see Note 1). The sample has one of two values: H = Not busy. The TI380C25 can become bus master if the grant condition is met. L = Busy. The TI380C25 cannot become bus master. SBCLK 65 I System bus clock. The TI380C25 requires SBCLK to synchronize its bus timings for all DMA transfers. Valid frequencies are 2 MHz – 33 MHz. SBHE / SRNW 79 I/O Intel Mode SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA; it is an input at all other times. H = System byte high not enabled (see Note 1) L = System byte high enabled SBHE / SRNW 79 I/O Motorola Mode SRNW is used for system read not write. SRNW serves as a control signal to indicate a read or write cycle. H = Read cycle (see Note 1) L = Write cycle SBRLS 49 I System bus release. SBRLS indicates to the TI380C25 that a higher-priority device requires the system bus. The value on SBRLS is ignored when the TI380C25 is not perfoming DMA. SBRLS is internally synchronized to SBCLK. H = The TI380C25 can hold onto the system bus (see Note 1). L = The TI380C25 should release the system bus upon completion of current DMA cycle. If the DMA transfer is not yet complete, the SIF rearbitrates for the system bus. SCS 48 I System chip select. SCS activates the system interface of the TI380C25 for a DIO read or write. H = Not selected (see Note 1) L = Selected SDBEN 80 O System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN is activated during both DIO and DMA. H = Keep external data buffers in the high-impedance state L = Cause external data buffers to begin driving data SDDIR 59 O System data direction. SDDIR provides the external data buffers with a signal indicating the direction the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the TI380C25). During DIO reads and DMA writes, SDDIR is high (data direction is out from the TI380C25). When the system interface is not involved in a DIO or DMA operation, SDDIR is high by default. DATA SDDIR DIRECTION DIO DMA H output read write L input write read † I = input, O = output NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch). |
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