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TAS3202PAGR Datasheet(PDF) 2 Page - Texas Instruments |
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TAS3202PAGR Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 66 page  DSP Core 8051 Microprocessor Core Oscillator DPLL Clock Divider 512Fs XTAL MCLK_IN 512Fs Slave Clock Generation Serial Audio Port LRCLK_OUT SCLK_OUT LRCLK_IN SCLK_IN SDOUT1 Stereo ADC Two Differential Stereo Analog Inputs Stereo DAC Differential Stereo Analog Output SCL1/SDA1 SCL2/SDA2 GPIO1/2 Master/Slave Power Supply AVDD DVDD 128Fs Volume Update Input Cross Bar Mixer Output Cross Bar Mixer SDIN1 SDIN2 Clocks Legend Digital Data Analog Data Internal Connection External Connection Control Registers External RAM 2K Code RAM 16K 8-Bit MCU Internal RAM 256 Data RAM 1K Upper Mem 768 Lower Mem Coefficient RAM 1.2K Code RAM 3K DSP Control Memory Interface Data Path I2C Control Interface Delay Memory 5.8K SDOUT2 TAS3202 SLES208B – JUNE 2009 – REVISED MARCH 2011 www.ti.com Figure 1-1. Expanded Functional Block Diagram 1.4 Ordering Information TA PLASTIC 64-PIN PQFP (PN)(1) 0°C to 70°C TAS3202PAG (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. 2 Introduction Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TAS3202 |
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