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SN55182-SP Datasheet(PDF) 2 Page - Texas Instruments |
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SN55182-SP Datasheet(HTML) 2 Page - Texas Instruments |
2 / 15 page LOGIC SYMBOL & 3 1IN+ 1 1IN− RT 2 4 1STRB RESP 5 1RTC 1OUT 6 11 2IN+ 13 2IN− 12 10 2STRB 9 2RTC 2OUT 8 1RT 2RT LOGIC DIAGRAM (POSITIVE LOGIC) 1OUT 3 1 2 5 4 1IN+ 1IN− 1RT 1RTC 1STRB 6 2OUT 11 13 12 9 10 2IN+ 2IN− 2RT 2RTC 2STRB 8 SN55182-SP SLLS874 – OCTOBER 2007 .............................................................................................................................................................................................. www.ti.com FUNCTION TABLE(1) INPUTS OUTPUT OUT STRB VID L X H H H H H L L (1) H = VI ≥ VIH min or VID more positive than VTH max L = VI ≤ VIL max or VID more negative than VTL max X = irrelevant This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the J, N, and W packages. Pin numbers shown are for the J, N, and W packages. 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN55182-SP |
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