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MSP430FG4619IPZR Datasheet(PDF) 10 Page - Texas Instruments |
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MSP430FG4619IPZR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 111 page  General-Purpose Register Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R12 R13 General-Purpose Register General-Purpose Register R6 R7 General-Purpose Register General-Purpose Register R8 R9 General-Purpose Register General-Purpose Register R10 R11 General-Purpose Register General-Purpose Register R14 R15 MSP430xG461x MIXED SIGNAL MICROCONTROLLER SLAS508I − APRIL 2006 − REVISED MARCH 2011 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The MSP430xG461x device family utilizes the MSP430X CPU and is completely backwards compatible with the MSP430 CPU. For a complete description of the MSP430X CPU, see the MSP430x4xx Family User’s Guide (SLAU056). instruction set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes. |
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