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MF5 Datasheet(PDF) 5 Page - Texas Instruments |
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MF5 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 18 page  Pin Description LP(14) BP(1) The second order lowpass bandpass NAPHP(2) and notchallpasshighpass outputs The LP and BP outputs can typically sink 1 mA and source 3 mA The NAPHP output can typically sink 15 mA and source 3 mA Each output typically swings to within 1V of each supply INV1(3) The inverting input of the summing op amp of the filter This is a high impedance input but the non-inverting input is internally tied to AGND making INV1 behave like a summing junction (low impedance current input) S1(4) S1 is a signal input pin used in the allpass filter configurations (see modes 4 and 5) The pin should be driven with a source impedance of less than 1 kX IfS1isnot driven with a signal it should be tied to AGND (mid-supply) SA(5) This pin activates a switch that connects one of the inputs of the filter’s second summer to either AGND (SA tied to Vb) or to the lowpass (LP) output (SA tied to Va) This offers the flexibility needed for configuring the filter in its various modes of operation 50100(9) This pin is used to set the internal clock to center frequency ratio (fCLK fo)ofthe filter By tying the pin to Va an fCLK fo ratio of about 501 (typically 5011 g 02%) is obtained Tying the 50100 pin to either AGND or Vb will set the fCLK fo ratio to about 1001 (typically 10004 g 02%) AGND(11) This is the analog ground pin This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation For a further discussion of mid-supply biasing techniques see the Applications Information (Section 32) For optimum filter performance a ‘‘clean’’ ground must be provided Va(6) Vb(10) These are the positive and negative supply pins The MF5 will operate over a total supply range of 8V to 14V Decoupling the supply pins with 01 mF capacitors is highly recommended CLK(8) This is the clock input for the filter CMOS or TTL logic level clocks can be accomodated by setting the L Sh pin to the levels described in the L Sh pin description For optimum filter performance a 50% duty cycle clock is recommended for clock frequencies greater than 200 kHz This gives each op amp the maximum amount of time to settle to a new sampled input L Sh(7) This pin allows the MF5 to accommodate either CMOS or TTL logic level clocks For dual supply operation (ie g5V) a CMOS or TTL logic level clock can be accepted if the L Sh pin is tied to mid-supply (AGND) which should be the system ground For single supply operation the L Sh pin should be tied to mid-supply (AGND) for a CMOS logic level clock The mid-supply bias should be a very low impedance node See Applications Information for biasing techniques For a TTL logic level clock the L Sh pin should be tied to Vb which should be the system ground INV2(12) This is the inverting input of the uncommitted op amp This is a very high impedance input but the non-inverting input is internally tied to AGND making INV2 behave like a summing junction (low-impedance current input) Vo2(13) This is the output of the uncommitted op amp It will typically sink 15 mA and source 30 mA It will typically swing to within 1V of each supply Typical Performance Characteristics Deviation of FCLK Fo vs Nominal Q Deviation of FCLK Fo vs Nominal Q OPAMP Output Voltage Swing vs Temperature TLH5066 – 3 4 |
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