Typical

Tested

Design

Parameter

Conditions

(Note 6)

Limit

Limit

Units

(Note 7)

(Note 8)

Output

BP LP pins

g

40

g

38

V

Swing (Min)

NAPHP pin

g

42

g

38

V

83

dB

Dynamic Range

(501 CLK ratio)

(Note 4)

80

dB

(1001 CLK ratio)

Maximum Output Short Circuit

Source

20

mA

Current (Note 5)

Sink

30

mA

Typical

Tested

Design

Parameter

Conditions

(Note 6)

Limit

Limit

Units

(Note 7)

(Note 8)

Gain Bandwidth Product

25

MHz

Output Voltage Swing (Min)

g

42

g

38

V

Slew Rate

70

V ms

DC Open-Loop Gain

80

db

Input Offset Voltage (Max)

g

50

g

20

mV

Input Bias Current

10

pA

Maximum Output

Source

20

mA

Short Circuit

Current (Note 5)

Sink

30

mA

MIN

s

Typical

Tested

Design

Parameter

Conditions

(Note 6)

Limit

Limit

Units

(Note 7)

(Note 8)

CMOS Clock

Min Logical ‘‘1’’

30

V

Input

Input Voltage

Max Logical ‘‘0’’

b

30

V

Input Voltage

Min Logical ‘‘1’’

80

V

Input Voltage

Max Logical ‘‘0’’

20

V

Input Voltage

TTL Clock

Min Logical ‘‘1’’

20

V

Input

Input Voltage

Max Logical ‘‘0’’

08

V

Input Voltage

Note 1

Note 2

Characteristics’’

Note 3

Note 4

the MF5 with a 501 CLK ratio and 280 mV rms for the MF5 with a 1001 CLK ratio

Note 5

The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to

the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting

that output to the positive supply These are the worst case conditions

Note 6

Typicals are at 25 C and represent most likely parametric norm

Note 7

Guaranteed and 100% tested

Note 8

Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels

3