Si8900/1/2

Rev. 1.0

11

4. ADC Data Transmission Modes

The master can access ADC read-only registers ADC_H and ADC_L using either Demand Mode or Burst Mode. In

Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode

(MODE = 0), the Si890x performs ADC conversions continuously.

Figure 5. ADC Demand Mode Operation

Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the

Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.)

Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC

conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART.

The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC

conversion data. The Si8901 (Figure 5B) ADC read transaction is identical to that of the Si8900 with the exception

read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the

transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two

times shorter versus the Si8900/01.

C)  Si8901 Demand Mode ADC Read

B)  Si8900 Demand Mode ADC Read 

Master to Slave

Slave to Master

CNFG_0

Command 

Byte

Master writes CNFG_0 

Command Byte to Si8900 Rx 

Master reads updated CNFG_0 and ADC 

Data From Si8900 (Tx output)

MODE = 1

ADC_H

ADC_L

CNFG_0

Command 

Byte

Master to Slave

Slave to Master

Master reads Slave Address, updated CNFG_0 

and ADC Data from Si8901 (SDA pin) 

MODE = 1

ADC_H

ADC_L

CNFG_0

Command 

Byte

CNFG_0

Command 

Byte

CNFG_0

Command 

Byte

D)  Si8902 Demand Mode ADC Read  

Master writes CNFG_0 

Command Byte to Si8902 SDI 

Master reads updated CNFG_0 and 

ADC Data from Si8902 SDO

Master to Slave

Slave to Master

MODE = 1

ADC_H

ADC_L

CNFG_0 

Command 

Byte

Slave Address 

Master writes Slave Address and 

CNFG_0 Command Byte to Si8901 SDA

The master must wait 8µS 

(track‐and‐hold time) before 

reading ADC data packet. 

Slave 

Address