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GC5325IZND Datasheet(PDF) 9 Page - Texas Instruments

Part # GC5325IZND
Description  GC5325 Wideband Digital Predistortion Transmit Processor
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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GC5325IZND Datasheet(HTML) 9 Page - Texas Instruments

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MPU Interface Guidelines
GC5325
www.ti.com .............................................................................................................................................................................................. SLWS215 – JANUARY 2009
Table 2. GC5325 TX Interface Options
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
TX (Single-Channel HSTL)
TX10, TX6, TX2, TX0, TX4, TX8, TX12, TX16, TX23, TX27,
DAC[15:0]P
O
DAC positive output
TX31, TX35, TX32, TX36, TX29, TX25
TX11, TX7, TX3, TX1, TX5, TX9, TX13, TX17, TX22, TX26,
DAC[15:0]N
O
DAC negative output
TX30, TX34, TX33, TX37, TX28, TX24
DACCLK
TX21
O
Clock to DAC
DACCLKC
TX20
O
Complementary clock to DAC
DACSYNCP
TX14
O
Positive output data sync
DACSYNCN
TX15
O
Negative output data sync
Table 3. GC5325 FB Interface Options
PIN FUNCTION
PIN NAME
I/O
DESCRIPTION
Feedback (Single-Channel SDR LVDS or DDR LVDS)
FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16, FB20,
ADC[15:0]P
I
ADC positive feedback from PA output
FB22, FB24, FB26, FB28, FB30, FB32, FB34
FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17, FB21,
ADC[15:0]N
I
ADC negative feedback from PA output
FB23, FB25, FB27, FB29, FB31, FB33, FB35
ADCCLK
FB0
I
Clock from ADC
ADCLKC
FB1
I
Complementary clock from ADC
Feedback (Single- or Dual-Channel DDR LVDS)
ADCA[7:0]P
FB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16
I
ADC-A positive feedback from PA output
ADCA[7:0]N
FB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17
I
ADC-A negative feedback from PA output
ADCACLK
FB0
I
Clock from ADC-A
ADCACLKC
FB1
I
Complementary clock from ADC-A
ADCB[7:0]P
FB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34
I
ADC-B positive feedback from PA output
ADCB[7:0]N
FB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35
I
ADC-B negative feedback from PA output
ADCBCLK
FB18
I
Clock from ADC-B
ADCBCLKC
FB19
I
Complementary clock from ADC-B
The following section describes the hardware interface between the recommended microprocessor, external
memory, and the GC5325. Users may select a microprocessor that meets their specific system requirements.
Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully
supported with host control and adaptation software. Figure 2 illustrates the hardware interface between the DSP
to GC5325 and SDRAM. The external memory is required to accommodate the computational efforts of the
adaptation algorithm. Although the system evaluation kit suggests dual parallel 64-Mb/PC133 (128-Mb) memory
modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are available. The processing
speed or convergence time of the adaptation algorithm is not strictly limited by the external memory speed rating.
The use of an external inverter, with minimal propagation delay, is required for OEB of the GC5325; this device is
necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in
the Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSP External
Memory Interface (EMIF) user's guide (SPRU711).
Copyright © 2009, Texas Instruments Incorporated
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