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DATA

CLK

Strobe

DRV8808

www.ti.com

SLVS857A

– DECEMBER 2009 – REVISED AUGUST 2011

Sixteen-bit serial data is shifted least significant bit (LSB) first into the serial data input (DATA) shift register on

the falling edge of the serial clock (CLK). After 16-bit data transfer, the strobe signal (Strobe) rising edge latches

all the shifted data. During the data transferring, Strobe voltage level is ok with L level or H level.

NOTE

During startup (VM rising), nSLEEP input is set HI, suppressing false data latching caused

by a rising edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms

after dc-dc regulators come up).

Setup Mode, Extended Setup Mode, Power-Down Mode

The motor output mode is configured through the SIP (DATA, CLK and STROBE) when nSLEEP = L. After set

up, the nSLEEP pin must be pulled high for normal motor drive control. The value on the DATA line at the

positive edge of STROBE when nSLEEP is low, selects whether the data is written to the Setup or Extended

Setup registers. Setup is selected for DATA = L; Extended Setup is selected for DATA = H.

The condition, which the device requires for set up (initialize), is after the nORT (Reset) output goes H level from

down and their outputs are high-impedance state. This device forces motor-driver functions to shut down for the

power-down mode, and is not damaged even if nSLEEP is asserted during motor driving.

Data is shifted at all times, regardless of nSLEEP. Care must be taken to ensure valid data has been shifted into

the internal shift register, before the STROBE rising edge, occurs while nSLEEP is LO.

Copyright

© 2009–2011, Texas Instruments Incorporated

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