High-Z

Enable,

Source

orSink

BLANK

ChargePump

Counter

NFAULT

MotorLead

ShortCondition

NormalDC

MotorCapacitance

DRV8800-Q1

DRV8801-Q1

www.ti.com

SLVSAS7

– FEBRUARY 2011

Figure 2. Overcurrent Control Timing

FUNCTIONAL DESCRIPTION

Device Operation

The DRV8800-Q1/DRV8801-Q1 is designed to drive one dc motor. The current through the output full-bridge

switches and all N-channel DMOS are regulated with a fixed off-time PWM control circuit.

Logic Inputs

the current to the input in case an overvoltage event occurs. Logic inputs are nSLEEP, MODE, PHASE, and

ENABLE. Voltages higher than 7 V on any logic input can cause damage to the input structure.

VREG (DRV8800-Q1 Only)

This output represents a measurement of the internal regulator voltage. This pin should be left disconnected. A

voltage of approximately 7.5 V can be measured at this pin.

VPROPI (DRV8801-Q1 Only)

This output offers an analog voltage proportional to the winding current. Voltage at this terminal is five times

greater than the motor winding current (VPROPI = 5

×I). VPROPI is meaningful only if there is a resistor

connected to the SENSE pin. If SENSE is connected to ground, VPROPI measures 0 V. During slow decay,

VPROPI outputs 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is

disabled.

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): DRV8800-Q1 DRV8801-Q1