SL74HCT74N datasheet(4/5 Pages) SLS

Part #	SL74HCT74N

Description	Dual D Flip-Flop with Set and Reset(High-Performance Silicon-Gate CMOS)

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Manufacturer	SLS [System Logic Semiconductor]

Direct Link	http://www.slsemicon.co.kr/e_index.htm

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SL74HCT74

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(V

CC =5.0 V

±10%,C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

25

°C

to

-55

°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

30

24

20

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

24

30

36

ns

tPLH, tPHL

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

24

30

36

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

15

19

22

ns

CIN

Maximum Input Capacitance

10

pF

Power Dissipation Capacitance (Per Enabled

Output)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

130

pF

TIMING REQUIREMENTS(V

CC =5.0 V

±10%,C

L=50pF,Input t r=tf=6.0 ns)

Guaranteed Limit

Symbol

Parameter

25

°C to-55°C

≤85°C

≤125°C

Unit

tsu

Minimum Setup Time, Data to Clock

(Figure 3)

15

19

22

ns

th

Minimum Hold Time, Clock to Data

(Figure 3)

3

ns

trec

Minimum Recovery Time, Set or Reset

Inactive to Clock (Figure 2)

6

8

9

ns

tw

Minimum Pulse Width, Clock (Figure

1)

15

19

22

ns

tw

Minimum Pulse Width, Set or Reset

(Figure 2)

15

19

22

ns

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

500

ns

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SL74HCT74N Datasheet(PDF) 4 Page - System Logic Semiconductor

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