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DLPC300ZVB Datasheet(PDF) 4 Page - Texas Instruments

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Part # DLPC300ZVB
Description  DLP짰 Digital Controller for the DLP3000 DMD
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC300ZVB Datasheet(HTML) 4 Page - Texas Instruments

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background image
bit 6
bit 5
bit 4
b
3
b2
b0
b1
bit 7
bit plane
256
128
64
32
16
24-bit RGB Image
8-bit Red Image
8-bit Green Image
8-bit Blue Image
8 Red Bit-Planes
8 Green Bit-Planes
8 Blue Bit-Planes
DLPC300
DLPS023A – JANUARY 2012 – REVISED JULY 2012
www.ti.com
Figure 3. Bit Slices
The length of each bit-plane in the time slot is weighted by the corresponding power of 2 of its binary
representation. This provides a binary pulse-width modulation of the image. For example, a 24-bit RGB input has
three colors with 8-bit depth each. Each color time slot is divided into eight bit-planes, with the sum of all bit
planes in the time slot equal to 256. See Figure 4 for an illustration of this partition of the bits in a frame.
Figure 4. Bit Partition in a Frame for an 8-Bit Color
Therefore, a single video frame is composed of a series of bit-planes. Because the DMD mirrors can be either on
or off, an image is created by turning on the mirrors corresponding to the bit set in a bit-plane. With the binary
pulse-width modulation, the intensity level of the color is reproduced by controlling the amount of time the mirror
is on. For a 24-bit RGB frame image inputted to the DLP300, the DLPC300 creates twenty-four bit planes, stores
them on the mDDR, and sends them to the DLP3000 DMD, one bit-plane at a time. Depending on the bit weight
of the bit-plane, the DLPC300 controls the time this bit-plane is exposed to light, controlling the intensity of the
bit-plane. To improve image quality in video frames, these bit-planes, time slots, and color frames are intertwined
and interleaved with spatial-temporal algorithms by the DLPC300.
For other applications where this image enhancement is not desired, the video processing algorithms can be
bypassed and replaced with a specific set of bit-planes. The bit-depth of the pattern is then allocated into the
corresponding time slots. Futhermore, an output trigger signal is also synchronized with these time slots to
indicate when the image is displayed. For structured light applications this mechanism provides the capability to
display a set of patterns and signal a camera to capture these patterns overlayed on an object.
4
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DLPC300


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