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LTM9004 Datasheet(PDF) 11 Page - Linear Technology |
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LTM9004 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 36 page  11 2270f LTC2270 PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1μF ceramic capacitors. Adjacent pins can share a bypass capacitor. VCM1 (Pin 2): Common Mode Bias Output, nominally equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs to channel 1. Bypass to ground with a 1μF ceramic capacitor. GND (Pins 3, 6, 14): ADC Power Ground. AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input. AIN1– (Pin 5): Channel 1 Negative Differential Analog Input. REFH (Pins 7, 9): ADC High Reference. See the Applica- tions Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 8, 10): ADC Low Reference. See the Applica- tions Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 11): Programming mode selection pin. Con- nect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or VDD and not be driven by a logic signal. AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input. AIN2– (Pin 13): Channel 2 Negative Differential Analog Input. VCM2 (Pin 15): Common Mode Bias Output, nominally equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs to channel 2. Bypass to ground with a 1μF ceramic capacitor. ENC+ (Pin 18): Encode Input. Conversion starts on the rising edge. ENC– (Pin 19): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 20): In serial programming mode, (PAR/SER = 0V), CS is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD),CScontrolstheclockdutycyclestabilizer (See Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 21): In serial programming mode, (PAR/SER = 0V), SCK is the Serial Interface Clock Input. In the parallel programming mode (PAR/SER = VDD), SCK controls the digital output mode. (See Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 22): In serial programming mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/ SER = VDD), SDI can be used together with SDO to power down the part (see Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 41): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 42): Output Driver Supply. Bypass to ground with a 0.1μF ceramic capacitor. SDO (Pin 61): In serial programming mode, (PAR/SER = 0V), SDO is the optional Serial Interface Data Output. Data on SDO is read back from the mode control regis- ters and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO can be used together with SDI to power down the part (see Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. PIN FUNCTIONS |
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Similar Description - LTM9004 |
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