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5962-0723001VXC Datasheet(PDF) 8 Page - Texas Instruments |
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5962-0723001VXC Datasheet(HTML) 8 Page - Texas Instruments |
8 / 41 page CDCM7005-SP SGLS390E – JULY 2009 – REVISED AUGUST 2012 www.ti.com DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VREF_IN = VCC/2, Y = VCC/2, tpho Phase offset (REF_IN to Y output)(5) 2.7 ns see Figure 13, Load = 10 pF tsk(p) LVCMOS pulse skew, see Figure 12 Crosspoint to VCC/2 load, see Figure 14 160 ps tpd(LH) Crosspoint to VCC/2, Propagation delay from VCXO_IN to Load = 10 pF, see Figure 14 (PLL 2.8 ns Yx, see Figure 12 tpd(HL) bypass mode) All outputs have the same divider ratio 80 LVCMOS single-ended output skew, tsk(o) ps see (6) and Figure 12 Outputs have different divider ratios 80 Duty cycle LVCMOS VCC/2 to VCC/2 49% 51% 20% to 80% of swing (load tslew-rate Output rise/fall slew rate 3.5 V/ns see Figure 14) LVPECL fclk Output frequency, see (7) and Figure 7 Load, see Figure 15 0 2000 MHz II LVPECL input current VI = 0 V or VCC ±20 µA VOH LVPECL high-level output voltage Load, See Figure 15 VCC–1.18 VCC–0.81 V VOL LVPECL low-level output voltage Load, See Figure 15 VCC–2 VCC–1.55 V |VOD| Differential output voltage See Figure 11 and load, see Figure 15 500 mV VREF_IN = VCC/2 to cross point of Y, tpho Phase offset (REF_IN to Y output)(6) 250 ps see Figure 13 tpd(LH) Propagation delay time, VCXO_IN to Cross point-to-cross point, load 615 ps Yx, see Figure 12 see Figure 15 tpd(HL) Cross point-to-cross point, load tsk(p) LVPECL pulse skew, see Figure 12 15 ps see Figure 15 Load see Figure 15, all outputs have the 20 same divider ratio tsk(o) LVPECL output skew(8) ps Load see Figure 15, outputs have 50 different divider ratios tr / tf Rise and fall time 20% to 80% of VOUTPP, see Figure 11 170 ps Input capacitance at VCXO_IN, CI 2.5 pF VCXO_IN LVCMOS-TO-LVPECL Output skew between LVCMOS and Cross point to VCC/2; load, tsk(P_C) 2 3.2 ns LVPECL outputs, see (9) and Figure 12 see Figure 14 and Figure 15 PLL ANALOG LOCK IOH High-level output current VCC = 3.6 V, VO = 1.8 V -150 –110 -80 µA IOL Low-level output current VCC = 3.6 V, VO = 1.8 V 80 110 150 µA High-impedance state output current IOZH LOCK VO = 3.6 V (PD is set low) 45 65 µA for PLL LOCK output(10) High-impedance state output current IOZL LOCK VO = 0 V (PD is set low) ±5 µA for PLL LOCK output(10) VIT+ Positive input threshold voltage VCC = min to max VCC×0.55 V VIT– Negative input threshold voltage VCC = min to max VCC×0.35 V PHASE DETECTOR fCPmax Maximum charge pump frequency Default PFD pulse width delay 100 MHz CHARGE PUMP Charge pump sink/source current ICP VCP = 0.5 VCC_CP ±0.2 ±3.9 mA range (11) (5) This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (6) The tsk(o) specification is only valid for equal loading of all outputs. (7) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. (8) The tsk(o) specification is only valid for equal loading of all outputs. (9) The phase of LVCMOS is lagging in reference to the phase of LVPECL. (10) Lock output has an 80-k Ω pulldown resistor. (11) Defined by SPI settings. 8 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s) :CDCM7005-SP |
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