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CDCE949QPWRQ1 Datasheet(PDF) 2 Page - Texas Instruments

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Part # CDCE949QPWRQ1
Description  PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE949QPWRQ1 Datasheet(HTML) 2 Page - Texas Instruments

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CDCE949-Q1
SCAS891 – FEBRUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CDCE949 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier,
and divider. It generates up to 9 output clocks from a single input frequency. Each output can be programmed
in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.
The CDCE949 has separate output supply pins, VDDOUT, of 2.5 V to 3.3 V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external
control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™,
Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as
27 MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This
is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically
adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application.
It is preset to a factory-default configuration (see the Default Device Configuration section). It can be
reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system
programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including
frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing
between low level or 3-state for the output-disable function.
The CDCE949 operates in a 1.8 V environment. It operates within a temprateure range of –40°C to 125°C.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 125°C
TSSOP – PW
Reel of 2000
CDCE949QPWRQ1
CDCE949Q
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE949-Q1


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