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CDC3S04YFFR Datasheet(PDF) 3 Page - Texas Instruments |
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CDC3S04YFFR Datasheet(HTML) 3 Page - Texas Instruments |
3 / 27 page CDC3S04 www.ti.com SCAS883B – OCTOBER 2009 – REVISED MAY 2011 FUNCTION SELECTION TABLES Table 1. Reset and Request (REQx) Conditions for Clock Outputs(1) RESET(2) PRIORITY BIT(3) CLK1 CLK2 CLK3 CLK4 0 Controlled by REQ2 Controlled by REQ3 0 On On 1 Controlled by REQ2INT Controlled by REQ3INT 0 Controlled by REQ1 Controlled by REQ2 Controlled by REQ3 Controlled by REQ4 1 1 Controlled by REQ1INT Controlled by REQ2INT Controlled by REQ3INT Controlled by REQ4INT (1) Shaded cells show the default setting after power up. (2) RESET resets REQ1PRIO/REQ4PRIO and REQ1INT/REQ4INT bits to their default values (CLK1/4 is ON) but does not change the remaining internal SW bits. During RESET, any I2C operation is blocked until RESET is deactivated. A minimum pulse duration of 500 ns must be applied to activate RESET (the internal glitch-filter suppresses spikes of typical 300 ns). (3) Priority bit defines if the external control pins (HW controlled) or the SW bits (SW controlled) have priority. It can be set in the configuration register, Byte 2, Bits 0 –3. Table 2. Request Signal Condition for Clock Outputs(1) REQx CLKx REQ-Signals(2) MCLK_REQ LDO(3) (REQ1/2/3/4) (CLK1/2/3/4) Active-low 0 Clock High On 1 Disabled to high Low (if all REQx are high) Off (if all REQx are high) 0 Disabled to high(4) Low (if all REQx are low) Off (if all REQx are low) Active-high 1 Clock(4) High On (1) Shaded cells show the default setting after power up. (2) Polarity of REQ1, REQ2, REQ3, and REQ4 are register-configurable via I2C (see Table 3, Byte 0, Bits 0 –3). Default setting is active-high. (3) The LDO is controlled by an on-chip decoder, but can also be SW controlled (see Table 3, Byte 2, Bits 4 –5). (4) CLK1 and CLK4 are ON after device power up (default condition). CLK2 and CLK3 are controlled by external REQ2 and REQ3, respectively. POWER GROUPS NAME DESCRIPTION VBAT Supply pin for LDO provided by main battery. LDO is not working if only VBAT is on. 1.8-V low-drop output voltage for external TCXO. LDO is enabled if VBAT and VDD_DIG are on and REQx or RESET is VLDO active (see Table 2). 1.8-V power supply for core logic and I2C logic. VDD_DIG must be supplied for correct device operation. Power up of VDD_DIG VDD_DIG resets the whole device to the default condition. 1.8-V power supply for sine-wave buffers. For correct sine-wave buffer function, all three power supplies (VBAT, VDD_DIG VDD_ANA and VDD_ANA) must be on. But, VDD_ANA can be switched on and off at any time. If off, the sine-wave outputs are switched to high-impedance. POWER-UP SEQUENCE The CDC3S04 is designed for sequence-less power up. VBAT, VDD_DIG, and VDD_ANA may be applied in any order. Recommended power-on sequence is VBAT first, followed by VDD_DIG and VDD_ANA. Recommended power-off sequence is in reverse order. Copyright © 2009–2011, Texas Instruments Incorporated 3 |
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