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BQ77908 Datasheet(PDF) 9 Page - Texas Instruments |
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BQ77908 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 56 page t su(BUF) bq77908 www.ti.com SLUSAI5D – APRIL 2011 – REVISED NOVEMBER 2011 ELECTRICAL CHARACTERISTICS (continued) Vcell(n) = 1.4 to 4.375 for all cells, TA = –25°C to 85ºC, BAT = 5.6 to 35 V; Typical values stated where TA = 25°C and BAT = 28.8 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CHARGER DETECTION (11) Voltage at CHGST pin, referenced to VSS, to determine VCHG_DET1 charger present (charger 5.6 V < BAT < 35 V 0.3 0.5 0.7 V insertion detected when voltage at CHGST pin > VCHG_DET1) LOAD REMOVAL DETECTION Voltage at DPCKN, referenced to VSS, with DSG FET disabled VOPEN_LOAD to detect load removal (load 5.6 V < BAT < 35 V 1.5 2 2.5 V removal detected when voltage at DPCKN < VOPEN_LOAD) Internal resistance between RDSG_GND 5.6 V < BAT < 35 V 1000 1500 3000 k Ω DPCKN and VSS EEPROM LIFETIME TDR Data retention 5.6 V < BAT < 35 V 10 years (11) Alternate charger detection options are available using the CPCKN pin. Contact TI for additional configuration versions. SERIAL COMMUNICATION INTERFACE (for Configuration Only) BAT = 5.6 V to 35 V, TA = –25°C to 85°C PARAMETER MIN MAX UNIT tr SCLK, SDATA rise time 1000 ns tf SCLK, SDATA fall time 300 ns tw(H) SCLK pulse duration, high 8 µs tw(L) SCLK pulse duration, low 10 µs tsu(STA) Setup time for START condition 9.4 µs th(STA) START condition hold time after which first clock pulse is generated 8 µs tsu(DAT) Data setup time 250 ns th(DAT) Data hold time 0 µs tsu(STOP) Setup time for STOP condition 8 µs tsu(BUF) Time the bus must be free before new transmission can start 9.4 µs tV Clock low to data out valid 900 ns th(CH) Data out hold time after clock low 0 ns fSCL Clock frequency 0 50 kHz Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): bq77908 |
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