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bq27505YZGT-J3 Datasheet(PDF) 3 Page - Texas Instruments |
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bq27505YZGT-J3 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 44 page CSP-12 (TOP VIEW) A 1 A 2 A 3 B 1 B 2 C 1 C 2 C 3 D 1 D 2 D 3 B 3 A 1 A 2 A 3 B 1 B 2 B 3 C 1 C 2 C 3 D 1 D 2 D 3 CSP-12 (BOTTOMVIEW) Not Recommended for New Designs bq27505-J3 www.ti.com SLUS986A – OCTOBER 2009 – REVISED FEBRUARY 2010 2 DEVICE INFORMATION 2.1 AVAILABLE OPTIONS PART NUMBER FIRMWARE VERSION PACKAGE(1) TA COMMUNICATION FORMAT TAPE & REEL QUANTITY bq27505YZGR-J3 3000 2.20 CSP-12 –40°C to 85°C I2C bq27505YZGT-J3 250 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2.2 DISSIPATION RATINGS POWER RATING DERATING FACTOR PACKAGE THERMAL RESISTANCE(1) (2) TA = 25°C ABOVE(1) (2) TA = 25°C YZG qJA = 89°C/W qJB = 35°C/W 1.1 W 12 mW/°C (1) Measured with high-K board. (2) Maximum power dissipation is a function of TJ(max), qJA and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/ qJA. 2.3 PIN ASSIGNMENT Table 2-1. PIN FUNCTIONS PIN TYPE(1) DESCRIPTION NAME NO. Analog input pin connected to the internal coulomb counter where SRP is nearest the PACK– connection. SRP A1 IA Connect to 5-m Ω to 20-mΩ sense resistor. Analog input pin connected to the internal coulomb counter where SRN is nearest the Vss connection. SRN B1 IA Connect to 5-m Ω to 20-mΩ sense resistor. Battery Low output indicator. Active high by default, though polarity can be configured through the BAT_LOW C1 O [BATL_POL] bit of Operation Configuration. Push-pull output. Vss D1 P Device ground Battery-good indicator. Active-low by default, though polarity can be configured through the [BATG_POL] bit BAT_GD A2 O of Operation Configuration. Push-pull output. SOC state interrupts output. Generate a pulse under the conditions specified by Table 5-5. Open drain SOC_INT B2 I/O output. BAT C2 I Cell-voltage measurement input. ADC input. Recommend 4.8V maximum for conversion accuracy. Vcc D2 P Processor power input. Decouple with minimum 0.1mF ceramic capacitor. Slave I2C serial communications data line for communication with system (Master). Open-drain I/O. Use with SDA A3 I/O 10k Ω pull-up resistor (typical). Slave I2C serial communications clock input line for communication with system (Master). Use with 10k Ω SCL B3 I pull-up resistor (typical). Battery-insertion detection input. Power pin for pack thermistor network. Thermistor-multiplexer control pin. BI/TOUT C3 I/O Use with pull-up resistor >1M Ω (1.8 MΩ typical). TS D3 IA Pack thermistor voltage sense (use 103AT-type thermistor). ADC input (1) I/O = Digital input/output, IA = Analog input, P = Power connection Copyright © 2009–2010, Texas Instruments Incorporated DEVICE INFORMATION 3 Submit Documentation Feedback |
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