Electronic Components Datasheet Search |
|
AFE4300 Datasheet(PDF) 6 Page - Texas Instruments |
|
|
AFE4300 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page SCLK STE SDIN SDOUT t SCLK t CSSC t SPWH t DIHD t SPWL t CSDOZ t DOHD t DOPD t SCCS t SCSC t CSH t CSDOD t DIST Hi-Z Hi-Z AFE4300 SBAS586A – JUNE 2012 – REVISED JUNE 2012 www.ti.com SPI TIMING CHARACTERISTICS Figure 1. Serial Interface Timing TIMING REQUIREMENTS: SERIAL INTERFACE TIMING At TA = 0°C to +70°C and VDD = 2 V to 3.6 V, unless otherwise noted. SYMBOL DESCRIPTION MIN MAX UNIT tCSSC STE low to first SCLK setup time(1) 100 ns tSCLK SCLK period 250 ns tSPWH SCLK pulse width high 100 ns tSPWL SCLK pulse width low 100 ns tDIST Valid SDIN to SCLK falling edge setup time 50 ns tDIHD Valid SDIN to SCLK falling edge hold time 50 ns tDOPD SCLK rising edge to valid new SDOUT propagation delay(2) 50 ns tDOHD SCLK rising edge to DOUT invalid hold time 0 ns tCSDOD STE low to SDOUT driven propagation delay 100 ns tCSDOZ STE high to SDOUT Hi-Z propagation delay 100 ns tCSH STE high pulse 200 ns tSCCS Final SCLK falling edge to STE high 100 ns (1) STE can be tied low. (2) DOUT load = 20 pF || 100 k Ω to DGND. 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): AFE4300 |
Similar Part No. - AFE4300 |
|
Similar Description - AFE4300 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |