54AC16823, 74AC16823

18BIT BUS INTERFACE FLIPFLOPS

WITH 3STATE OUTPUTS

SCAS243A − APRIL 1991 − REVISED APRIL 1996

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Widebus

 Family

Wider Address/Data Paths or Buses With

Parity

PCB Layout

Minimizes High-Speed Switching Noise

CMOS) 1-

µm Process

at 125

°C

Shrink Small-Outline (DL) Package Using

25-mil Center-to-Center Pin Spacings and

380-mil Fine-Pitch Ceramic Flat (WD)

Package Using 25-mil Center-to-Center Pin

Spacings

description

These 18-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing wider buffer

registers, I/O ports, parity bus interfacing, and

working registers.

The ’AC16823 can be used as two 9-bit flip-flops

or one 18-bit flip-flop. With the clock-enable

(CLKEN) input low, the D-type flip-flops enter data

on the low-to-high transitions of the clock. Taking

CLKEN high disables the clock buffer, thus

latching the outputs. Taking the clear (CLR) input

low causes the Q outputs to go low independently

of the clock.

The output enable (OE) input can be used to place the outputs in either a normal logic state (high or low) or a

high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The 74AC16823 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count

and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16374 is characterized for operation over the full military temperature range of −55

°C to 125°C. The

74AC16823 is characterized for operation from −40

°C to 85°C.

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1CLR

1OE

1Q1

GND

1Q2

1Q3

1Q4

1Q5

1Q6

GND

1Q7

1Q8

1Q9

2Q1

2Q2

2Q3

GND

2Q4

2Q5

2Q6

2Q7

2Q8

GND

2Q9

2OE

2CLR

1CLK

1CLKEN

1D1

GND

1D2

1D3

1D4

1D5

1D6

GND

1D7

1D8

1D9

2D1

2D2

2D3

GND

2D4

2D5

2D6

2D7

2D8

GND

2D9

2CLKEN

2CLK

54AC16823 . . . WD PACKAGE

74AC16823 . . . DL PACKAGE

(TOP VIEW)

Copyright

 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.