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74AC11593DW Datasheet(PDF) 6 Page - Texas Instruments |
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74AC11593DW Datasheet(HTML) 6 Page - Texas Instruments |
6 / 11 page 74AC11593 8BIT BINARY COUNTER WITH 3STATE I/O INPUT REGISTERS SCAS202 − MARCH 1992 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 2−6 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX UNIT MIN MAX MIN MAX UNIT fclock Clock frequency, CCK or RCK 40 40 MHz CCK high or low 6 6 RCK high or low 6 6 tw Pulse duration RCK high or low 4.5 4.5 ns tw Pulse duration CCLR low 7.5 7.5 ns CLOAD low 6.1 6.1 CCKEN low before CCK ↑ 5.2 5.2 CCKEN high before CCK ↑ 6.4 6.4 tsu Setup time CCLR high before CCK ↑ 1.7 1.7 ns tsu Setup time CLOAD high before CCK ↑ 8.2 8.2 ns RCK ↑ before CLOAD↑{ 11.1 11.1 Data A thru H before RCK ↑ 2.3 2.3 th Hold time Data A thru H after RCK ↑ 0.5 0.5 ns th Hold time All others 0.2 0.2 ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX UNIT MIN MAX MIN MAX UNIT fclock Clock frequency, CCK or RCK 70 70 MHz CCK high or low 5 5 RCK high or low 5 5 tw Pulse duration RCK high or low 4.5 4.5 ns tw Pulse duration CCLR low 5 5 ns CLOAD low 4.7 4.7 CCKEN low before CCK ↑ 3.1 3.1 CCKEN high before CCK ↑ 4.3 4.3 tsu Setup time CCLR high before CCK ↑ 1.1 1.1 ns tsu Setup time CLOAD high before CCK ↑ 5.4 5.4 ns RCK ↑ before CLOAD↑{ 7.8 7.8 Data A thru H before RCK ↑ 2 2 th Hold time Data A thru H after RCK ↑ 1.1 1.1 ns th Hold time All others 0.8 0.8 ns † This time insures the data saved by RCK↑ will also be loaded into the counter. |
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