Connection Diagrams

Pin Assignment for

DIP SOIC and Flatpak

TLF9525 – 2

Pin Assignment

for LCC

TLF9525 – 3

Unit LoadingFan Out

54F74F

Pin Names

Description

UL

HIGHLOW

Data Inputs

1010

CE

Clock Enable (Active LOW)

1010

CP

Clock Pulse Input

1010

Data Outputs

50333

b

1 mA20 mA

Mode Select-Function Table

Operating Mode

Inputs

Output

CP

CE

Load ‘‘1’’

L

Ih

H

Load ‘‘0’’

L

II

L

Hold

L

h

X

No Change

(Do Nothing)

X

H

X

No Change

the LOW-to-HIGH Clock Transition

the LOW-to-HIGH Clock Transition

Logic Diagram

TLF9525 – 5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2