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C8051F333-GM Datasheet(PDF) 4 Page - Silicon Laboratories |
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C8051F333-GM Datasheet(HTML) 4 Page - Silicon Laboratories |
4 / 300 page C8051F39x/37x 4 Preliminary Rev. 0.71 17. Memory Organization ............................................................................................ 91 17.1. Program Memory............................................................................................. 92 17.1.1. MOVX Instruction and Program Memory ................................................ 92 17.2. Data Memory ................................................................................................... 92 17.2.1. Internal RAM ........................................................................................... 92 17.2.1.1. General Purpose Registers ............................................................ 93 17.2.1.2. Bit Addressable Locations .............................................................. 93 17.2.1.3. Stack ............................................................................................ 93 17.2.2. External RAM .......................................................................................... 93 18. Device ID Registers ............................................................................................... 95 19. Special Function Registers................................................................................... 99 19.1. SFR Paging ..................................................................................................... 99 19.2. Interrupts and Automatic SFR Paging ............................................................. 99 19.3. SFR Page Stack Example ............................................................................. 101 20. Interrupts .............................................................................................................. 115 20.1. MCU Interrupt Sources and Vectors.............................................................. 116 20.1.1. Interrupt Priorities.................................................................................. 116 20.1.2. Interrupt Latency ................................................................................... 116 20.2. Interrupt Register Descriptions ...................................................................... 118 20.3. External Interrupts INT0 and INT1................................................................. 126 21. Flash Memory....................................................................................................... 129 21.1. Programming The Flash Memory .................................................................. 129 21.1.1. Flash Lock and Key Functions .............................................................. 129 21.1.2. Flash Erase Procedure ......................................................................... 129 21.1.3. Flash Write Procedure .......................................................................... 130 21.2. Non-volatile Data Storage ............................................................................. 130 21.3. Security Options ............................................................................................ 131 21.4. Flash Write and Erase Guidelines ................................................................. 133 21.4.1. VDD Maintenance and the VDD Monitor ................................................ 133 21.4.2. PSWE Maintenance .............................................................................. 133 21.4.3. System Clock ........................................................................................ 134 22. EEPROM (C8051F37x) ......................................................................................... 138 22.1. EEPROM Communication Protocol.............................................................. 138 22.1.1. Slave Address Byte............................................................................... 139 22.1.2. Acknowledgement (ACK) ...................................................................... 139 22.1.3. Not-Acknowledgement (NACK)............................................................. 139 22.1.4. Reset..................................................................................................... 139 22.2. Write Operation ............................................................................................. 140 22.3. Read Operation ............................................................................................. 141 22.3.1. Current Address Read .......................................................................... 141 22.3.2. Selective Address Read........................................................................ 143 23. Cyclic Redundancy Check Unit (CRC0)............................................................. 145 23.1. CRC Algorithm............................................................................................... 145 23.2. Preparing for a CRC Calculation ................................................................... 147 23.3. Performing a CRC Calculation ...................................................................... 147 |
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