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AD9518-0 Datasheet(PDF) 39 Page - Analog Devices |
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AD9518-0 Datasheet(HTML) 39 Page - Analog Devices |
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39 / 64 page  Data Sheet AD9518-0 Rev. C | Page 39 of 64 If the AD9518 clock outputs must be synchronized to each other, a SYNC is required upon exiting power-down (see the Synchronizing the Outputs—Sync Function section). A VCO calibration is not required when exiting power-down. PLL Power-Down The PLL section of the AD9518 can be selectively powered down. There are three PLL operating modes set by Register 0x010[1:0], as shown in Table 44. In asynchronous power-down mode, the device powers down as soon as the registers are updated. In synchronous power-down mode, the PLL power-down is gated by the charge pump to prevent unwanted frequency jumps. The device goes into power-down on the occurrence of the next charge pump event after the registers are updated. Distribution Power-Down The distribution section can be powered down by writing Register 0x230[1] = 1b. This turns off the bias to the distribution section. If the LVPECL power-down mode is normal operation (00b), it is possible for a low impedance load on that LVPECL output to draw significant current during this power-down. If the LVPECL power-down mode is set to 11b, the LVPECL output is not protected from reverse bias and may be damaged under certain termination conditions. Individual Clock Output Power-Down Any of the clock distribution outputs can be powered down individually by writing to the appropriate registers. The register map details the individual power-down settings for each output. The LVPECL outputs have multiple power-down modes (see Table 45), which give some flexibility in dealing with the various output termination conditions. When the mode is set to 10b, the LVPECL output is protected from reverse bias to 2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions. This setting also affects the operation when the distribution block is powered down with Register 0x230[1] = 1b (see the Distribution Power-Down section). Individual Circuit Block Power-Down Other AD9518 circuit blocks (such as CLK, REF1, and REF2) can be powered down individually. This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed. |
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