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ADS1205IRGER Datasheet(PDF) 7 Page - Texas Instruments |
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ADS1205IRGER Datasheet(HTML) 7 Page - Texas Instruments |
7 / 29 page ADS1205 SBAS312B − JANUARY 2005 − REVISED AUGUST 2007 www.ti.com 7 PARAMETER MEASUREMENT INFORMATION CLKOUT OUT x t C1 t W2 t D4 t D3 t C2 t W1 t D1 t D2 CLKIN Figure 1. ADS1205 Timing Diagram TIMING REQUIREMENTS(1) over recommended operating free-air temperature range at −40 °C to +85°C, AVDD = 5V, and BVDD = 2.7 to 5V, unless otherwise noted. PARAMETER MIN MAX UNIT tC1 CLKIN period: (CLKSEL = 0) 41.6(2) 1000 ns tW1 CLKIN high time: (CLKSEL = 0) 10 tC1 − 10 ns tC2 CLKOUT period using internal oscillator (CLKSEL = 1) 83 125 ns CLKOUT period using external clock (CLKSEL = 0) 2 × tC1 ns tW2 CLKOUT high time (tC2/2) − 5 (tC2/2) + 5 ns tD1 CLKOUT rising edge delay after CLKIN rising edge: (CLKOUT = 0) 0 10 ns tD2 CLKOUT falling edge delay after CLKIN rising edge: (CLKOUT = 0) 0 10 ns tD3 Data valid delay after rising edge of CLKOUT (CLKSEL = 1) (tC2/4) − 8 (tC2/4) + 8 ns tD4 Data valid delay after rising edge of CLKOUT (CLKSEL = 0) tW1 − 3 tW1 + 7 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 1. (2) With reduced accuracy, the minimum clock period can go down to 30ns. |
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