Electronic Components Datasheet Search |
|
CY3672-USB Datasheet(PDF) 1 Page - Cypress Semiconductor |
|
CY3672-USB Datasheet(HTML) 1 Page - Cypress Semiconductor |
1 / 15 page CY23FP12 200 MHz Field Programmable Zero Delay Buffer Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-07246 Rev. *G Revised January 18, 2011 Features ■ Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop (PLL) or fanout buffer configuration ■ 10 MHz to 200 MHz operating range ■ Split 2.5 V or 3.3 V outputs ■ Two LVCMOS reference inputs ■ Twelve low skew outputs ❐ 35 ps typical output-to-output skew (same frequency) ■ 110 ps typical cycle-cycle jitter (same frequency) ■ Three-stateable outputs ■ Less than 50 μA shutdown current ■ Spread aware ■ 28-pin SSOP ■ 3.3 V operation ■ Industrial temperature available Functional Description The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distri- bution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors. The CY23FP12 is fully programmable through volume or prototype programmers, enabling the user to define an appli- cation-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions listed in Table 2, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature enables the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12 also features a proprietary auto power down circuit that shuts down the device in case of a REF failure, resulting in less than 50 μA of current draw. The CY23FP12 provides 12 outputs grouped in two banks with separate power supply pins which can be connected indepen- dently to either a 2.5 V or a 3.3 V rail. Selectable reference input is a fault tolerance feature which enables glitch-free switch over to a secondary clock source when REFSEL is asserted/deasserted. FBK ÷M ÷N 100 to 400MHz PLL CLKA1 CLKA3 CLKA2 REF2 REFSEL CLKA4 CLKA5 CLKB1 CLKB3 CLKB2 CLKB4 CLKB5 VDDA VSSA VDDB VSSB ÷2 ÷3 ÷4 ÷X CLKA0 VDDC VSSC ÷1 Lock Detect Test Logic REF1 CLKB0 S[2:1] Function Selection Logic Block Diagram [+] Feedback |
Similar Part No. - CY3672-USB |
|
Similar Description - CY3672-USB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |