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CY23FP12OXIT Datasheet(PDF) 9 Page - Cypress Semiconductor |
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CY23FP12OXIT Datasheet(HTML) 9 Page - Cypress Semiconductor |
9 / 15 page CY23FP12 Document #: 38-07246 Rev. *G Page 9 of 15 Switching Waveforms Figure 3. Duty Cycle Timing Figure 4. All Outputs Rise/Fall Time TTB Total timing budget,[8,9] Bank A and B same frequency Outputs at 200 MHz, tracking skew not included – – 650 ps Total timing budget, Bank A and B different frequency – – 850 t5 Output to output skew[5] All outputs equally loaded – 35[10] 200 ps Bank to bank skew Same frequency – – 200 Bank to bank skew Different frequency – – 400 Bank to bank skew Different voltage, same frequency – – 400 t6 Input to output skew (static phase offset)[5] Measured at VDD/2, REF to FBK – 0 250 ps t7 Device-to-device skew[5] Measured at VDD/2 – 0 500 ps tJ Cycle-to-cycle jitter[5] (Peak) Banks A and B at same frequency – 110[11] 200 ps Cycle-to-cycle jitter[5] (Peak) Banks A and B at different frequencies – – 400 tTSK Tracking skew Input reference clock at < 50-KHz modulation with ±3.75% spread – – 200 ps tLOCK PLL lock time[5] Stable power supply, valid clock at REF – – 1.0 ms tLD Inserted loop delay Max loop delay for PLL Lock (stable frequency) –– 7 ns Max loop delay to meet Tracking Skew Spec – – 4 ns Switching Characteristics [5] Parameter Description Test Conditions Min Typ Max Unit Notes 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency. 10. Same frequency, 15pF load, high drive. 11. Same frequency, 15pF load, low drive. [+] Feedback |
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