Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY14C512PA Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY14C512PA
Description  512-Kbit (64 K 횞 8) SPI nvSRAM with Real Time Clock
Download  42 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14C512PA Datasheet(HTML) 6 Page - Cypress Semiconductor

Back Button CY14C512PA_12 Datasheet HTML 2Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 3Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 4Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 5Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 6Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 7Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 8Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 9Page - Cypress Semiconductor CY14C512PA_12 Datasheet HTML 10Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 42 page
background image
CY14C512PA
CY14B512PA
CY14E512PA
Document Number: 001-65268 Rev. *D
Page 6 of 42
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X512PA provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X512PA can run at speeds up to
104 MHz except RDRTC and READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. CY14X512PA supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X512PA operates as a slave device and may share the SPI
bus with multiple CY14X512PA devices or other SPI devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW.
The CY14X512PA is selected when the CS pin is LOW. When
the device is not selected, data through the SI pin is ignored and
the serial output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14X512PA allows SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X512PA has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 3 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
CY14X512PA requires a 2-byte address for any read or write
operation.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X512PA uses the standard opcodes for memory accesses.
In addition to the memory accesses, CY14X512PA provides
additional opcodes for the nvSRAM specific functions: STORE,
RECALL, AutoStore Enable, and AutoStore Disable. Refer to
Table 1 on page 9 for details on opcodes.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS and the SO pin remains tri-stated.
Status Register
CY14X512PA has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 3 on page 10.


Similar Part No. - CY14C512PA_12

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY14C512PA CYPRESS-CY14C512PA_13 Datasheet
1Mb / 42P
   512-Kbit (64 K x 8) SPI nvSRAM
More results

Similar Description - CY14C512PA_12

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY14B512P CYPRESS-CY14B512P Datasheet
1Mb / 36P
   512-Kbit (64 K 횞 8) Serial (SPI) nvSRAM with Real Time Clock
CY14B512P CYPRESS-CY14B512P_12 Datasheet
1Mb / 34P
   512-Kbit (64 K 횞 8) Serial (SPI) nvSRAM with Real Time Clock
CY14C064PA CYPRESS-CY14C064PA_12 Datasheet
1Mb / 43P
   64-Kbit (8 K 횞 8) SPI nvSRAM with Real Time Clock
CY14C512I CYPRESS-CY14C512I_12 Datasheet
1Mb / 40P
   512-Kbit (64 K 횞 8) Serial (I2C) nvSRAM with Real Time Clock
CY14B512P CYPRESS-CY14B512P_13 Datasheet
1Mb / 35P
   512-Kbit (64 K x 8) Serial (SPI) nvSRAM with Real Time Clock
CY14C512Q CYPRESS-CY14C512Q_12 Datasheet
1Mb / 32P
   512-Kbit (64 K 횞 8) SPI nvSRAM
CY14C064PA CYPRESS-CY14C064PA Datasheet
1Mb / 43P
   64-Kbit (8 K x 8) SPI nvSRAM with Real Time Clock with Real Time Clock
CY14C064PA CYPRESS-CY14C064PA_13 Datasheet
1Mb / 43P
   64-Kbit (8 K x 8) SPI nvSRAM with Real Time Clock
CY14B512Q1 CYPRESS-CY14B512Q1_12 Datasheet
1Mb / 27P
   512-Kbit (64 K 횞 8) Serial (SPI) nvSRAM
CY14C256PA CYPRESS-CY14C256PA_12 Datasheet
1Mb / 43P
   256-Kbit (32 K 횞 8) SPI nvSRAM with Real Time Clock
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com