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CY14B512J2-SXI Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY14B512J2-SXI
Description  512-Kbit (64 K 횞 8) Serial (I2C) nvSRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY14B512J2-SXI Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY14C512J
CY14B512J
CY14E512J
Document Number: 001-65232 Rev. *D
Page 7 of 30
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X512J
reserves two sets of upper 4 MSBs [7:4] in the slave device
address field for accessing Memory and Control Registers. The
accessing mechanism is described in Memory Slave Device on
page 7.
The nvSRAM product provides two different functionalities:
Memory and Control Registers functions (such as serial number
and product ID). The two functions of the device are accessed
through different slave device addresses. The first four most
significant bits [7:4] in the device address register are used to
select between the nvSRAM functions.
Memory Slave Device
The nvSRAM device is selected for Read/Write if the master
issues the slave address as 1010b followed by two/three bits of
device select. For CY14X512J1/J3, the device select is three bits
and for CY14X512J2, it is two bits with the third bit don’t care. If
the slave address sent by the master matches with the Memory
Slave device address, then depending on the R/W bit of the slave
address, data is either read from (R/W = ‘1’) or written to
(R/W = ‘0’) the nvSRAM.
The address length for CY14X512J is 16 bits and thus it requires
two address bytes to map the entire memory address location.
The dedicated two address bytes represent bit A0 to A15.
Control Registers Slave Device
The Control Registers Slave device includes the Serial Number,
Product ID, Memory Control and Command Register.
The nvSRAM Control Register Slave device is selected for
Read/Write if the master issues the Slave address as 0011b
followed by two/three bits of device select. For CY14X512J1/J3
device select is 3 bits and for CY14X512J2 it is two bits with third
bit don’t care. If slave address sent by the master matches with
the Memory Slave device address then depending on the R/W
bit of the slave address, data is either read from (R/W = ‘1’) or
written to (R/W = ‘0’) the nvSRAM.
Table 1. Slave device Addressing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
nvSRAM
Function Select
CY14X512J Slave Devices
1
0
1
0
Device Select ID
R/W Selects Memory
Memory, 64 K × 8
0
0
1
1
Device Select ID
R/W Selects Control
Registers
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
- Command Register, 1 × 8
Figure 8. Memory Slave Device Address
handbook, halfpage
R/W
LSB
MSB
Slave ID
10
1
0
A2
A0/X
A1
Device Select
Figure 9. Control Registers Slave Device Address
Table 2. Control Registers Map
Address
Description Read/Write
Details
0x00
Memory
Control
Register
Read/Write Contains
Block
Protect Bits and Serial
Number Lock bit
0x01
Serial Number
8 Bytes
Read/Write
(Read only
when SNL
is set)
Programmable Serial
Number. Locked by
setting
the
Serial
Number lock bit in the
Memory
Control
Register to ‘1’.
0x02
0x03
0x04
0x05
0x06
0x07
0x08
handbook, halfpage
R/W
LSB
MSB
Slave ID
0
0
1
1
A2
A0/X
A1
Device Select


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