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CY14B256LA-SZ45XIT Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14B256LA-SZ45XIT Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 22 page CY14B256LA Document Number: 001-54707 Rev. *I Page 6 of 22 During any STORE operation, regardless of how it is initiated, the CY14B256LA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low-power condition (VCC<VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven low by the HSB driver. Software STORE Data is transferred from SRAM to the nonvolatile memory by a software address sequence. The CY14B256LA Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: 1. Read address 0x0E38 valid READ 2. Read address 0x31C7 valid READ 3. Read address 0x03E0 valid READ 4. Read address 0x3C1F valid READ 5. Read address 0x303F valid READ 6. Read address 0x0FC0 initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x0E38 valid READ 2. Read address 0x31C7 valid READ 3. Read address 0x03E0 valid READ 4. Read address 0x3C1F valid READ 5. Read address 0x303F valid READ 6. Read address 0x0C63 initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Table 1. Mode Selection CE WE OE A14–A0[6] Mode I/O Power H X X X Not selected Output high Z Standby L H L X Read SRAM Output data Active L L X X Write SRAM Input data Active L H L 0x0E38 0x31C7 0x03E0 0x3C1F 0x303F 0x0B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[7] Notes 6. While there are 15 address lines on the CY14B256LA, only the lower 14 are used to control software modes. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. |
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