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CY14C256PA Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY14C256PA Datasheet(HTML) 5 Page - Cypress Semiconductor |
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5 / 43 page  CY14C256PA CY14B256PA CY14E256PA Document Number: 001-65281 Rev. *E Page 5 of 43 to complete the Store. This will corrupt the data stored in nvSRAM, Status Register as well as the serial number and it will unlock the SNL bit. To resume normal functionality, the WRSR instruction must be issued to update the nonvolatile bits BP0, BP1, and WPEN in the Status Register. Figure 2 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 31 for the size of the VCAP. Figure 2. AutoStore Mode Software STORE Operation Software STORE allows the user to trigger a STORE operation through a special SPI instruction. STORE operation is initiated by executing STORE instruction regardless of whether or not a write has been performed since the last NV operation. A STORE cycle takes tSTORE time to complete, during which all the memory accesses to nvSRAM are inhibited. The RDY bit of the Status Register or the HSB pin may be polled to find the Ready/Busy status of the nvSRAM. After the tSTORE cycle time is completed, the SRAM is activated again for read and write operations. Hardware STORE and HSB pin Operation The HSB pin in CY14X256PA is used to control and acknowledge STORE operations. If no STORE/RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14X256PA conditionally initiates a STORE operation after tDELAY duration. A STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle. Reads and Writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by an internal 100 k pull-up resistor. Note For successful last data byte STORE, a hardware STORE should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. The HSB pin must be left unconnected if not used. RECALL Operation A RECALL operation transfers the data stored in the nonvolatile QuantumTrap elements to the SRAM. In CY14X256PA, a RECALL may be initiated in two ways: Hardware RECALL, initiated on power-up and Software RECALL, initiated by a SPI RECALL instruction. Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL cycle is in progress. The RECALL operation does not alter the data in the nonvolatile elements. Hardware RECALL (Power-Up) During power-up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated, which transfers the content of nonvolatile memory on to the SRAM. The data would previously have been stored on the nonvolatile memory through a STORE sequence. A Power-Up RECALL cycle takes tFA time to complete and the memory access is disabled during this time. HSB pin is used to detect the Ready status of the device. Software RECALL Software RECALL allows you to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. In CY14X256PA, this can be done by issuing a RECALL instruction in SPI. A Software RECALL takes tRECALL time to complete during which all memory accesses to nvSRAM are inhibited. The controller must provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions. Disabling and Enabling AutoStore If the application does not require the AutoStore feature, it can be disabled in CY14X256PA by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power-down. AutoStore can be re enabled by using the ASENB instruction. However, these operations are not nonvolatile and if you need this setting to survive the power cycle, a STORE operation must be performed following AutoStore Disable or Enable operation. Note CY14X256PA comes from the factory with AutoStore Enabled and 0x00 written in all cells. If AutoStore is disabled and VCAP is not required, then the VCAP pin must be left open. The VCAP pin must never be connected to ground. The Power-Up RECALL operation cannot be disabled in any case. 0.1uF VCC VCAP CS VCAP VSS VCC |
Similar Part No. - CY14C256PA_12 |
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Similar Description - CY14C256PA_12 |
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