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CY14B101KA-SP25XI Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY14B101KA-SP25XI Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 34 page  CY14B101KA CY14B101MA 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-42880 Rev. *K Revised August 14, 2012 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Features ■ 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25 ns and 45 ns access times ❐ Internally organized as 128 K × 8 (CY14B101KA) or 64 K × 16 (CY14B101MA) ❐ Hands off automatic STORE on power-down with only a small capacitor ❐ STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power-down ❐ RECALL to SRAM initiated on power-up or by software ■ High reliability ❐ Infinite Read, Write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ 20 year data retention ■ Real time clock (RTC) ❐ Full featured real time clock ❐ Watchdog timer ❐ Clock alarm with programmable interrupts ❐ Capacitor or battery backup for RTC ❐ Backup current of 0.35 µA (Typ) ■ Industry standard configurations ❐ Single 3 V +20%, –10% operation ❐ Industrial temperature ■ Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-pin shrink small outline package (SSOP) ■ Pb-free and restriction of hazardous substances (RoHS) compliant Functional Description The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit nvSRAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control. STATIC RAM ARRAY 1024 X 1024 R O W D E C O D E R COLUMN I/O COLUMN DEC I N P U T B U F F E R S POWER CONTROL STORE/RECALL CONTROL Quatrum Trap 1024 X 1024 STORE RECALL V CC V CA P HSB A 0 A1 A 2 A3 A4 A10 A11 SOFTWARE DETECT A 14 - A2 OE CE WE BHE BLE A 5 A 6 A 7 A 8 A 9 A 12 A 13 A 14 A 15 A 16 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 RTC MUX A 16- A0 X out X in INT V RTCbat V RTCcap Logic Block Diagram[1, 2, 3] Notes 1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. |
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