CY8C21123, CY8C21223, CY8C21323

Document Number: 38-12022 Rev. *U

Page 9 of 44

Table 4. Pin Definitions – CY8C21223 16-Pin QFN with no E-Pad[3]

Pin

No.

Type

Pin

Name

Description

Figure 5. CY8C21223 16-Pin QFN

Digital

Analog

1

I/O

I

P0[3]

Analog column mux input

2

I/O

I

P0[1]

Analog column mux input

3

I/O

P1[7]

4

I/O

P1[5]

5

I/O

P1[3]

6

I/O

P1[1]

7

Power

Ground connection

8

I/O

P1[0]

9

I/O

P1[6]

10

I/O

P1[4]

EXTCLK

11

Input

XRES

Active high external reset with internal

pull-down

12

I/O

I

P0[4]

13

Power

Supply voltage

14

I/O

I

P0[7]

Analog column mux input

15

I/O

I

P0[5]

Analog column mux input

16

NC

No Connection. Pin must be left floating

LEGEND A = Analog, I = Input, and O = Output.

QFN

(Top View)

1

2

3

4

12

11

10

9

XRES

P1[4]

P1[6]

AI, P0[3]

AI, P0[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

Notes

3. These are the ISSP pins, which are not high Z at POR (power on reset). See the PSoC Technical Reference Manual for details.

4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

must be electrically floated and not connected to any other signal.