CY7C09089V/99V

CY7C09179V/99V

Document #: 38-06043 Rev. *F

Page 7 of 28

Selection Guide

Description

CY7C09179V

-6[10]

CY7C09099V

-7[10]

CY7C09199V

-9

CY7C09089V/99V

CY7C09179V

-12

100

83

67

50

Max. Access Time (ns) (Clock to Data,

Pipelined)

6.5

7.5

9

12

175

155

135

115

(Both Ports TTL Level)

25

25

20

20

(Both Ports CMOS Level)

10

10

10

10

Pin Definitions

Left Port

Right Port

Description

Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to

access the part using an externally supplied address. Asserting this signal LOW also loads

the burst counter with the address present on the address pins.

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its

respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted

LOW.

Counter Reset Input. Asserting this signal LOW resets the burst address counter of its

respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.

Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during

read operations.

Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.

For read operations, assert this pin HIGH.

Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.

For pipelined mode operation, assert this pin HIGH.

GND

Ground Input.

NC

No Connect.

Power Input.

Note

10. See page 9 and page 10 for Load Conditions.

[+] Feedback