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CY7C2568XV18-633BZXC Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7C2568XV18-633BZXC
Description  72-Mbit DDR II Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C2568XV18-633BZXC Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C2568XV18, CY7C2570XV18
Document Number: 001-70206 Rev. *B
Page 5 of 29
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output-
Synchronous
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q[x:0] are automatically tri-stated.
CY7C2568XV18
 DQ[17:0]
CY7C2570XV18
 DQ[35:0]
LD
Input-
Synchronous
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
 Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C2568XV18
 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2570XV18
 BWS0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 4 M × 18 (2 arrays each of 2 M × 18) for CY7C2568XV18, and 2 M × 36 (2 arrays each of
1 M × 36) for CY7C2570XV18. The address pins (A) can be assigned any bit order.
R/W
Input-
Synchronous
Synchronous Read or Write input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
ODT [2]
On-Die
Termination
input pin
On-Die Termination Input. This pin is used for On-Die termination of the input signals. ODT range
selection is made during power up initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175
< RQ < 350 (where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175
< RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
Note
2. On-Die Termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.


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